Title

A Digital Transmitter Architecture with Enhanced Delay, Power and Noise Performance for Sensors and IoT Applications

Document Type

Book Chapter

Publication Date

1-2019

Subject: LCSH

Internet of things, Telecommunication systems, Artificial intelligence -- Technological innovations -- Congresses

Disciplines

Computer Engineering | Computer Sciences | Electrical and Computer Engineering

Abstract

Many communication systems require very low power usage, low latency or both. Examples are sensor networks, IoT applications, extremely delay sensitive communications (e.g., equity trading), etc. In this paper, we propose a baseband transmitter architecture based on Look-Up Tables (LUT) that achieves better SQNR performance with considerably less processing delay with all other parameters being equal. We show the effect of bit-width resolution on the performance. This architecture lends itself well to all forms of transmitter realization, such as hardware (ASIC or FPGA), firmware or software, providing faster processing at lower cycles or hardware resources.

DOI

10.1007/978-3-030-02683-7_67

Publisher Citation

Sarraf M., Forati F. (2019) A Digital Transmitter Architecture with Enhanced Delay, Power and Noise Performance for Sensors and IoT Applications. In: Arai K., Bhatia R., Kapoor S. (eds) Proceedings of the Future Technologies Conference (FTC) 2018, Vol. 2. FTC 2018. Advances in Intelligent Systems and Computing, vol 881. Springer, Cham, pp.925-932. ISBN: 978-3-030-02682-0

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